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The 80C320 provides another optimizing feature which allows many programs to execute faster: The dual Data Pointer. The 80C320 has two data pointers. The default data pointer is the standard DPTR which the 8052 supports. In your program makes no effort to use the second DPTR, the standard 8052 DPTR will be used. Thus existing programs will run without change. However, a new data pointer (called DPTR1), exists at
DPH1 (84h) and DPL1 (85h).
All references to DPTR use the currently selected data pointer--again, by default, the 80C320 uses the traditional 8052 DPTR. However, you may select DPTR1 by setting bit 0 of the new SFR DPS (DPTR Select at 86h). If bit 0 is clear, the standard DPTR will be used. If bit 0 is set, DPTR1 will be used in all instructions that refer to DPTR.
A common use of the DPTR in a standard 8052 is to copy data from one area of RAM to another. For example, you may wish to copy data from Extended RAM 2000h-20FFh to Extended RAM 3500h-35FFh. Using standard 8052 SFRs and code this could be coded in the following manner. Note that the number of cycles are based on 80C320 operation, not 8052 operation.
MOV R0,#20h ;High-byte of SourceAddress
MOV R1,#00h ;Low-byte of Source Address
MOV R2,#35h ;High-byte of Destination Address
MOV R3,#00h ;Low-byte of Destination Address
MOV R4,#64 ;Counter of # of characters to copy
LOOP:
MOV DPH,R0 ;Load high-byte of source address 2 cycles
MOV DPL,R1 ;Load low-byte of source address 2 cycles
MOVX A,@DPTR ;Read the byte from source memory 2 cycles
INC DPTR ;Increment the source memory pointer 3 cycles
MOV R0,DPH ;Save high-byte of source address 2 cycles
MOV R1,DPL ;Save low-byte of source address 2 cycles
MOV DPH,R2 ;Load high-byte of destination address 2 cycles
MOV DPL,R3 ;Load low-byte of destination address 2 cycles
MOVX @DPTR,A ;Save the byte to destination memory 2 cycles
INC DPTR ;Increment the destination memory pointer 3 cycles
MOV R2,DPH ;Save high-byte of destination address 2 cycles
MOV R3,DPL ;Save low-byte of destination address 2 cycles
DJNZ R4,LOOP ;Copy until R4=0 3 cycles
In all, the copy cycle requires 29 cycles per byte copied. In this case, 64 bytes would require 1856 instruction cycles. However, observe the code taking advantage of the 80C320s dual DPTR:
MOV DPS,#01h ;Make sure were on DPTR1
MOV DPTR,#3500h ;Load the destination address into DPTR1
DEC DPS ;Now DPS=0, so weve selected the default DPTR
MOV DPTR,#2000h ;Load the source address into DPTR
MOV R0,#64 ;Set our character counter
LOOP:
MOVX A,@DPTR ;Read the source byte 2 cycles
INC DPTR ;Increment the source pointer 3 cycles
INC DPS ;Now DPS=1 so were using DPTR1 2 cycles
MOVX @DPTR,A ;Write the value to the destination 2 cycles
INC DPTR ;Increment the destination pointer 3 cycles
DEC DPS ;Now DPS=0 so were using DPTR 2 cycles
DJNZ R0,LOOP ;Copy until R0=0 3 cycles
In this case, the copy cycle requires only 17 cycles. To copy the 64 bytes the dual-pointer process will require 1088 cycles. Compared to the 1856 cycles required by the normal approach, we see that using the dual DPTR accomplishes the same work in about 58% of the time. Additionally, we only need 1 "R" register in the process (to keep track of the number of characters copied) as opposed to 5 "R" registers in the original approach.
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80C320 -
Chapter
3 (WatchDog)
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