Microprocessor without Interlocked Pipeline Stages
<processor> (MIPS) A project at Stanford University intended to simplify
processor design by eliminating hardware interlocks between the five pipeline
stages. This means that only single execution cycle instructions can access the
thirty two 32-bit general registers, so that the compiler can schedule them to
avoid conflicts. This also means that LOAD/STORE and branch instructions have a
one-cycle delay to account for. However, because of the importance of multiply
and divide instructions, a special HI/LO pair of multiply/divide registers exist
which do have hardware interlocks, since these take several cycles to execute
and complicate instruction scheduling.
The project eventually lead to the commercial MIPS R2000 processor.
(1995-02-09)
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Microprocessor without Interlocked Pipeline Stages
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