RS flip-flop ==>
SR flip-flop
<hardware> (Or "RS flip-flop") A "set/reset" flip-flop in which
activating the "S" input will switch it to one stable state and activating the
"R" input will switch it to the other state.
The outputs of a basic SR flip-flop change whenever its R or S inputs change
appropriately. A clocked SR flip-flop has an extra clock input which enables or
disables the other two inputs. When they are disabled the outputs remain
constant.
If we connect two clocked SR flip-flops so that the Q and /Q outputs of the
first, "master" flip-flop drive the S and R inputs of the second, "slave"
flip-flop, and we drive the slave's clock input with an inverted version of the
master's clock, then we have an edge-triggered RS flip-flop. The external R and
S inputs of this device are latched on one edge (transition) of the clock (e.g.
the falling edge) and the outputs will only change on the next opposite (rising)
edge.
If both R and S inputs are active (when enabled), a race condition occurs and
the outputs will be in an indeterminate state. A JK flip-flop avoids this
possibility.
http://www.play-hookey.com/digital/logic4.html.
(1997-05-15)
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