<architecture> A technique which attempts to minimise the time a
processor spends waiting for instructions to be fetched from memory.
Instructions following the one currently being executed are loaded into a
prefetch queue when the processor's external bus is otherwise idle. If the
processor executes a branch instruction or receives an interrupt then the queue
must be flushed and reloaded from the new address.
Instruction prefetch is often combined with pipelining in an attempt to keep the
By 1995 most processors used prefetching, e.g. Motorola 680x0, Intel 80x86.
[First processors using prefetch?]
Institut National de Recherche en Informatique et
Automatique « Instruction Address Register «
instruction mnemonic « instruction prefetch »
instruction scheduling » instruction set »
instruction set architecture